Process for manufacturing semiconductor devices by implantation and diffusion

ABSTRACT

A process for manufacturing semiconductor devices according to the present invention comprises a step for thermally oxidizing semiconductor substrates (1), (12), to form first and second oxide films (24), (25) on one main surface and on another main surface thereof, respectively; a step for selectively implanting impurity inons via said first oxide film (24) to form elements in said semiconductor substrates (1), (12); a step for successively forming a film (30) that constitutes a source of impurity diffusion and a protective film (31) on said second oxide film (25); and a step of common heat-treatment for forming predetermined diffused layers (17), (18) on said one main surface of said semiconductor substrates (1), (12) by diffusing at least one kind of the impurity ions that are implanted, and for forming a diffused layer on said another main surface of the semiconductor substrates (1), (12) by diffusing impurities contained in the film (30) that constitutes said source of impurity diffusion into said semiconductor substrates (1), (12) via said second oxide film (25). 
     This makes it possible to effectively remove impurity atoms such as heavy metals present in the semiconductor substrate (1) and to perform the gettering of very fine defects. Further, the protective film (31) prevents adverse effects caused by the heat-treatment that is effected for forming diffused layers (17), (18). Therefore, a semiconductor device having improved reliability can be produced. Moreover, the manufacturing steps can be simplified, and various impurities can be used to form elements, presenting great convenience from the standpoint of production.

DESCRIPTION

1. Technical Field

The present invention relates to a process for manufacturingsemiconductor devices which permits the elimination of impurity atomssuch as heavy metals present in semiconductor substrates to be used forthe formation of semiconductor devices and the gettering of very finedefects.

2. Background Art

So far the above gettering has been performed by the followingprocedures in a conventional process for manufacturing a semiconductordevice, as shown in, e.g., FIGS. 1A to 1E. As shown in FIG. 1A, bothmain surfaces of, e.g., a p-type silicon substrate 1 are thermallyoxidized to form SiO₂ films 2 and 3 thereon. As shown in FIG. 1B, theSiO₂ film 3 on the lower surface of the silicon substrate 1 is thenremoved by an etching solution such as an HF-based solution. In thiscase, the SiO₂ film 2 is covered in advance with a photoresist (notshown) so that the film 2 is prevented from being etched.

After the photoresist is removed from the SiO₂ film 2, the resultantstructure is heated to a high temperature of 1,000° C. or more in an O₂atmosphere by using POCl₃ as a source of impurity diffusion, therebyperforming impurity diffusion. As a result, a phosphorus diffused layer4 is formed on the lower surface of the p-type silicon substrate 1, asshown in FIG. lC. At the same time, P₂ O₅ -based PSG(phosphorus-silica-glass) films 5 and 6 are formed on the phosphorusdiffused layer 4 and the SiO₂ film 2 on the upper surface of thesubstrate, respectively.

As shown in FIG. 1D, an SiO₂ film 7 is deposited by a CVD method on thePSG film 5 formed on the lower surface side. Thereafter, as shown inFIG. 1E, a photoresist 8 is applied to the SiO₂ film 7.

After a photoresist (not shown) is applied to the PSG film 6 on theupper surface side, the photoresist film is patterned in a predeterminedshape. Using this photoresist pattern as a mask, the PSG film 6 and theSiO₂ film 2 are etched using an HF-based etching solution to define anelement formation region and an element isolation region. Duringetching, the SiO₂ film 7 and the PSG film 5 are prevented from beingetched owing to the presence of the photoresist 8. A predeterminedmanufacturing process such as a bipolar IC manufacturing process is thenperformed to prepare a semiconductor device.

In the step of FIG. 1D, if after the formation of the SiO₂ film 7 an Si₃N₄ film having an etching resistant property against the HF-basedetching solution is formed thereon, it becomes unnecessary to form thephotoresist 8 in FIG. 1E.

According to the conventional manufacturing process described above, thegettering can effectively be performed owing to the presence of thephosphorus diffused layer 4 formed on the lower surface of the p-typesilicon substrate 1. At the same time, the SiO₂ film 7 can prevent anout diffusion of phosphorus from the phosphorus diffused layer 4 and thePSG film 5 in a heat-treatment at a high temperature in the stepsfollowing the step of FIG. 1E. According to the manufacturing processdescribed above, however, the steps in FIGS. 1A to 1E are required onlyfor the gettering. Accordingly, such a process has a drawback that thenumber of steps required for manufacturing the semiconductor device isincreased, thereby making the manufacturing process undesirably complex.

A process for manufacturing a bipolar IC, as shown in FIGS. 2A and 2B,is known as a process for manufacturing the semiconductor device, whicheliminates the above drawback. According to this process, as shown inFIG. 2A, an n⁺ -type buried layer 11 is formed in, e.g., a p-typesilicon substrate 1, and an n-type silicon epitaxial growth layer 12 isformed on the p-type silicon substrate 1. Thereafter, p⁺ -type isolationdiffused regions 13 and 14, and a p-type base region 15 are formed. AnSiO₂ film 16 is then formed on the surface of the silicon epitaxialgrowth layer 12. The predetermined portions of the SiO₂ film 16 areetched to form openings 16a and 16b.

In the same manner as described in connection with FIG. 1C, POCl₃ isused as a source of impurity diffusion, and the resultant structure isheated in an O₂ atmosphere at a high temperature of 1,000° C. or more todiffuse phosphorus ions via the openings 16a and 16b with the result ofthe formation of an n⁺ -type emitter region 17 and an n⁺ -type collectorelectrode region 18, respectively, as shown in FIG. 2B. At the sametime, a gettering phosphorus diffused layer 4 is formed on the lowersurface of the p-type silicon substrate 1. In this case, a P₂ O₅ -basedPSG film 19 is formed on the SiO₂ film 16, the emitter region 17, andthe collector electrode region 18. A P₂ O₅ -based PSG film 20 issimilarly formed on the phosphorus diffused layer 4. The n-type siliconepitaxial growth layer 12, which is present between the base region 15and the buried layer 11, constitutes a collector region 21.

According to the above manufacturing process shown in FIGS. 2A and 2B,the gettering phosphorus diffused layer 4 can be formed by diffusion forforming the emitter region 17. Therefore, as compared with themanufacturing steps shown in FIGS. 1A to 1E, the manufacturing processcan be simplified. However, if atoms of the type other than phosphorus,that is, arsenic (As) atoms are used to form the emitter region 17, themanufacturing process shown in FIGS. 2A and 2B cannot be used. Inaddition, since it is difficult to etch only the PSG film 19, the PSGfilm 19 is inevitably left in the finished product. This PSG filmabsorbs moisture and undesirably degrades reliability of thesemiconductor device.

DISCLOSURE OF INVENTION

It is an object of the present invention to provide a process formanufacturing a semiconductor device, which eliminates theabove-described conventional drawbacks.

The process for manufacturing semiconductor devices according to thepresent invention comprises a step for thermally oxidizing semiconductorsubstrates to form first and second oxide films on one main surface andon another main surface thereof, respectively; a step for selectivelyimplanting impurity ions via said first oxide film to form elements insaid semiconductor substrates; a step for successively forming a filmthat constitutes a source of impurity diffusion and a protective film onsaid second oxide film; and a step of common heat-treatment for formingpredetermined diffused layers on said one main surface of saidsemiconductor substrates by diffusing at least one kind of the impurityions that are implanted, and for forming a diffused layer on saidanother main surface of said semiconductor substrates by diffusingimpurities contained in the film that constitues said source of impuritydiffusion into said semiconductor substrates via said second oxide film.This makes it possible to effectively perform the gettering of very finedefects and to prevent adverse effects caused by the heat-treatment.Therefore, a semiconductor device having improved reliability can beproduced. Moreover, the manufacturing steps are relatively simple, andvarious impurities can be used to form elements, presenting greatconvenience from the standpoint of production.

Impurities for forming the above elements may be boron, phosphorus,arsenic, or other impurities, depending on the conductivity types oflayers to be formed by diffusion.

For the above film that constitutes a source of impurity diffusion, aPSG film and any other film may be used.

The above protective film may be an SiO₂ film or any other film if onlythe out diffusion of the impurity contained in the film whichconstitutes the source of impurity diffusion can be prevented.

The thickness of the first oxide film is not critical, if only theimpurity ions can be implanted in the semiconductor substrate via thefirst oxide film. The thickness of the second oxide film is also notcritical, if only the impurity ions contained in the film whichconstitutes the source of impurity diffusion can be diffused in thesemiconductor substrate through the second oxide film. Preferably, thethicknesses of the first and second oxide films are in the range of 50to 500 Å.

Depending on semiconductor devices to be manufactured, the abovesemiconductor substrate may be an n- or p-type silicon substrate, asubstrate of any other material, or substrate having a silicon layer orany other semiconductor layer on the silicon substrate.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1E are sectional views showing one example of the sequentialsteps of the conventional process for manufacturing a semiconductordevice;

FIGS. 2A and 2B are sectional views showing one example of thesequential steps of the conventional process for manufacturing a bipolarIC; and

FIGS. 3A to 3G are sectional views showing one embodiment by thesequential steps wherein a process for manufacturing a semiconductordevice according to the present invention is applied to the fabricationof a bipolar IC.

BEST MODE FOR CARRYING OUT THE INVENTION

One embodiment will now be described with reference to the accompanyingdrawings wherein a process for manufacturing a semiconductor deviceaccording to the present invention is applied to the fabrication of abipolar IC.

As shown in FIG. 3A, following the same procedures as in FIG. 2A, an n⁺-type buried layer 11 is formed in a p-type silicon substrate 1, and ann-type silicon epitaxial growth layer 12 is formed thereon. The surfaceof the silicon epitaxial growth layer 12 and the surface of the p-typesilicon substrate 1 are thermally oxidized to form 150 Å-thick SiO₂films 24 and 25 thereon. Damages to the silicon epitaxial growth layer12 during ion implantation described hereinafter can be reduced owing tothe presence of the SiO₂ films 24 and 25. At the same time, thechannelling of the doped ions can be prevented, and, in addition, thenitrogenation of the surface of the silicon epitaxial growth layer 12during heat-treatment in an N₂ atmosphere described hereinafter can beprevented.

A photoresist (not shown) is then applied to the SiO₂ film 24 and ispatterned in a predetermined shaped. Using this photoresist pattern as amask, boron (B) is ion-implanted in a high concentration into thesilicon epitaxial growth layer 12 via the SiO₂ film 24. After the abovephotoresist is removed, the resultant structure is subjected to theheat-treatment at a high temperature of about 1,000° C. in the N₂atmosphere. As a result, p⁺ -type isolation diffused regions 13 and 14reaching the p-type silicon substrate 1 are formed, as shown in FIG. 3B.A photoresist (not shown) is applied to the SiO₂ film 24 and ispatterned in a predetermined shape so as to form a base region 15described hereinafter. Thereafter, using the photoresist pattern as amask, boron ions are implanted into the silicon epitaxial growth layer12 at predetermined conditions. After the photoresist pattern isremoved, a photoresist pattern corresponding to a grafted base region 26described hereinafter is formed using the same photoresist process asdescribed above. By using this photoresist pattern as a mask, boron ionsare again implanted into the silicon epitaxial growth layer 12 atpredetermined conditions. After the photoresist pattern is removed, theresultant structure is subjected to the heat-treatment at a relativelylow temperature of 1,000° C. or less in the N₂ atmosphere toelectrically activate the implanted boron ions, thereby diffusing theions in the direction of depth. As a result, a p-type base region 15 anda p⁺ -type grafted base region 26 are formed, as shown in FIG. 3C.

The photoresist process described above is repeated to form apredetermined photoresist pattern on the SiO₂ film 24. Using thisphotoresist pattern as a mask, arsenic ions are implanted into thesilicon epitaxial growth layer 12 at predetermined conditions, therebyforming ion-implanted layer 27 and 28, as shown in FIG. 3D.

As shown in FIG. 3E, a relatively thick SiO₂ film 29 is formed on theSiO₂ film 24 by the CVD method.

As shown in FIG. 3F, a PSG film 30 having a phosphorus concentration of,e.g., 6.9% by weight and a thickness of 2,000 Å and an SiO₂ film 31having a thickness of 3,000 Å are sequentially formed by the CVD methodon the SiO₂ film 25 formed on the lower surface of the p-type siliconsubstrate 1. At the time of the deposition of the PSG film 30 and theSiO₂ film 31, the substrate must be placed on a sample holder in a CVDapparatus in order that the SiO₂ film 25 formed on the lower surface ofthe p-type silicon substrate 1 faces upward. The silicon epitaxialgrowth layer 12 may therefore be damaged when it is brought into contactwith the holder. However, this can be eliminated by the presence of therelatively thick SiO₂ film 29.

When the heat-treatment is performed in the N₂ atmosphere at a hightemperature of about 1,000° C., the arsenic ions contained in theion-implanted layers 27 and 28 are electrically activated, and theactivated arsenic ions are diffused in the direction of depth to form ann⁺ -type emitter region 17 and an n⁺ -type collector electrode region18, as shown in FIG. 3G. Similarly, the phosphorus ions contained in thePSG film 30 pass through the SiO₂ film 25 and are diffused in the lowersurface of the p-type silicon substrate 1, thereby forming a phosphorusdiffused layer 4. The above heat-treatment allows the diffusion ofphosphorus ions also in the SiO₂ film 25, so that the SiO₂ film 25 isconverted into a PSG film. This PSG film and the PSG film 30 formed bythe CVD method are represented together as the PSG film 30 in FIG. 3G.In this case, the n-type silicon epitaxial growth layer 12, which ispresent between the base region 15 and the buried layer 11, constitutesa collector region 21.

Thereafter, parts of the portions of the SiO₂ films 29 and 24, whichcorrespond to the grafted base region 26, the emitter region 17, and thecollector electrode region 18, are etched to form respective openings(not shown). Electrodes are formed on the base region 15, the emitterregion 17 and the collector region 21 via these openings, and the usualfabrication process of the bipolar IC is then performed to prepare adesired bipolar IC. When the electrode forming openings are formed byetching, the SiO₂ film 31 and the PSG film 30 formed on the lowersurface of the p-type silicon substrate 1 are also etched to expose thephosphorus diffused layer 4. In the steps following the etching step,only the heat-treatment at a low temperature of 750° C. or less isperformed, and thus phosphorus out diffusion is substantiallynegligible.

In order to evaluate reliability of the bipolar IC manufactured in theabove embodiment, a BT test was performed in such a way that a reversebias voltage is applied to the junction between the emitter and the baseat 175° C. for a predetermined period of time. The values of h_(FE)before and after the test were measured. Even after a 552-hour BT test,the changes in h_(FE) were within the range of ±3%. For comparison, thesame BT test as described above was performed for a bipolar IC having nophosphorus diffused layer 4. In this case, the h_(FE) of, for example,130 before the test was greatly changed to 80 after the test. As isapparent from these test results, the reliability of the bipolar ICmanufactured in the above embodiment is far better than that of thebipolar IC having no phosphorus diffused layer. This indicates that thegettering has effectively been performed by the phosphorus diffusedlayer 4 formed on the lower surface of the p-type silicon substrate 1.The best reliability was obtained when a sheet resistance (correspondingto a phosphorus concentration) of the phosphorus diffused layer 4 was 20Ω/□.)

According to the above embodiment, the common heat-treatment in the stepof FIG. 3G is performed to form the emitter region 17 and the collectorelectrode region 18, and, at the same time, to form the getteringphosphorus diffused layer 4 on the lower surface of the p-type siliconsubstrate 1. Therefore, the manufacturing steps can be simplified ascompared with the conventional fabrication process shown in FIGS. 1A to1E. In the step of FIG. 3G the phosphorus ions contained in the PSG film30 are diffused in the lower surface of the p-type silicon substrate 1via the SiO₂ film 25 to form the phosphorus diffused layer 4. So, it isnot necessary to etch the SiO₂ film 25, which would not otherwise berequired, thus further simplifying the manufacturing steps.

According to the embodiment described above, the PSG film 30 is used asa source of impurity diffusion to form the phosphorus diffused layer 4,thus presenting the following advantage. In the conventional fabricationprocess shown in FIGS. 2A and 2B the phosphorus diffused layer 4 isformed by a thermal diffusion method using POCl₃ as a source of impuritydiffusion, as described above, and the PSG film 19 (FIG. 2B) formedduring the thermal diffusion is therefore left in the finished productto cause degradation of moisture resistance. However, according to thisembodiment, the above problem is completely solved. In addition, animpurity for forming the emitter region 17 may be arsenic which cannotbe used in the conventional fabrication process in FIGS. 2A and 2B.

In the above embodiment, the protective film comprising the SiO₂ film 31is formed on the PSG film 30 in the step shown in FIG. 3F. Therefore,the out diffusion of phosphorus ions from the PSG film 30 during thehigh-temperature heat-treatment in the step of FIG. 3G can beeffectively prevented.

In the above embodiment there has been described the case wherein theprocess for manufacturing a semiconductor device is applied to thefabrication of the bipolar IC. However, the method of the presentinvention may also be applied to the fabrication of other semiconductordevices such as MOSICs and CCDs.

I claim:
 1. A process for manufacturing a semiconductor device,characterized by comprising a step of thermally oxidizing semiconductorsubstrates of opposite conductivity types to form first and second oxidefilms on one main surface and on another main surface thereof,respectively; a step of selectively implanting impurity ions via saidfirst oxide film to form diffused zones in said semiconductorsubstrates; a step of successively forming a film that constitutes asource of impurity diffusion of opposite conductivity type and aprotective film confined to said second oxide film; and a step of commonheat-treatment for forming predetermined diffused layers on said onemain surface of said semiconductor substrates by diffusing at least onekind of the impurity ions that are implanted, and for forming a diffusedlayer on said another main surface of said semiconductor substrates bydiffusing impurities contained in the film that constitutes said sourceof impurity diffusion into said semiconductor substrates via said secondoxide film.